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AD9125 minimum DAC rate with internal PLL

Question asked by rmccourt on Sep 17, 2012
Latest reply on Sep 18, 2012 by Tguy

We're using an AD9125 DAC on one of our boards, with the DAC clock being sourced from the internal PLL, locked to an 80 MHz reference. We'd like to run the DAC in 2x interpolation mode at 160 MHz, but it looks like the internal dividers in the PLL can only go down to 250 MHz (/4 with a min VCO freq of 1 GHz).


Is there any way to get additional division between the VCO and the DACCLK?


Thanks -