I use the AD9959 with the Single-Bit Serial 3-wire interface.
According the datasheet Rev. B page 31 of 44:
- the data written to the AD9959 are sampled on the rising edge of SCLK with 2.2ns setup and 0 ns hold time. This seems OK to me
- for the data to be read from the AD9959 there is mentioned that the data valid minimum time is 12ns relative to the falling edge of SCLK.
- is the value for tDV of 12 ns correct?
- if yes, how does this work together with a clock cycle time of 5 ns?
- which edge shifts out the data of SDO? rising or falling edge?
Checking the figure 47 on page 35 of 44 pretend that the falling edge of SCLK causes the change from D7 to D6
but it also pretend that the rising edge of SCLK causes the change from D1 to D0
Thanks for your answers