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AD9889B problem with output to monitor

Question asked by MIKE-LS on Sep 13, 2012
Latest reply on Sep 19, 2012 by cvaughn



I have development kit with FPGA and AD9889B for support HDMI-PHY.

I generate color bars picture from FPGA with separate DE, HSYNC and VSYNC signals with 74.25 MHz pixel frequency, but monitor displays only "No signal" message. Where is my errors?




Parameters of generator in FPGA:

HSync length: 40

HSync front porch: 110

HSync back porch: 220

VSync length: 5

VSync front porch: 5

VSync back porch: 21

Resolution: 720p


Configure of AD9889B registers (excerpt of configuration file, because i can configure device from PC):

First hex value (from left to right) - address, second - value. Addresses look strange, because i can access only for 32-bit aligned.

And real AD9889B acess adresses in comments.

# Configuration device

# ========================

# Power-up the Tx

master_write_8 $jtag_master 0x104 0x10; # write to 0x41 reg


# Fixed registers that must be set on power up

master_write_8 $jtag_master 0x28 0x00; # write to 0x0A reg

master_write_8 $jtag_master 0x260 0x07; # write to 0x98 reg

master_write_8 $jtag_master 0x270 0x38; # write to 0x9C reg

master_write_8 $jtag_master 0x274 0x01; # write to 0x9D reg

master_write_8 $jtag_master 0x288 0x84; # write to 0xA2 reg ?

master_write_8 $jtag_master 0x28C 0x84; # write to 0xA3 reg ?

master_write_8 $jtag_master 0x2EC 0xFF; # write to 0xBB reg


# Set up the video mode

master_write_8 $jtag_master 0x54 0x00; # write to 0x15 reg

master_write_8 $jtag_master 0x58 0x00; # write to 0x16 reg

master_write_8 $jtag_master 0x5C 0x02; # write to 0x17 reg


# HDCP & HDMI Video mode

# HDCP disable; HDMI mode - HDMI

master_write_8 $jtag_master 0x2BC 0x06; # write to 0xAF reg


# Audio mode

# I2S disable

master_write_8 $jtag_master 0x30 0x00; # write to 0x0C reg