I am using the ADUC7020 in spi slave mode withtout interrupt.
Just by checking the register SPISTA for the RX and TX .
I am using 8 bytes packets with clock phase =1 and clock polarity =1.
The master provides clock patterns based on 8 falling edges and 8 rising edges.
KNowing that if i expect a answer of n bytes, i have to provide the TX register with one command + dummy data in order to provide the clock, i observe very erratic data on the RX register.
Is there any advice or known tricks about the SPI management for this target?