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100Hz to 1.25MHz signal generation with AD9952

Question asked by trioflex on Sep 8, 2012
Latest reply on Sep 18, 2012 by trioflex

Hi

 

we are in prototyping and test stage with an larger design hat involves over 30 ADI IC's (over 20 different ones!) - one part of the design is sinus signal generation with single frequency range span of 100Hz to 1.25MHz (output +-10V single ended, capacitive load drive up to 10nF) , for this task we use:

 

AD9952 followed by two stages of differential low pass filters (cut off frequency 1MHz) implemented with AD8132, followed by: AD8251 doing differential to single ended conversion and applying gain of 1,2,4 or 8 (8 being used mostly), followed by AD5543 which applies Gain adjustment followed by ADA4004 performing I to V conversion and adding Offset generated by AD5422

 

AD9952 is clocked from master clock circuit implemented with AD9912 (1GHz clock from 25MHz crystal) designed to generate clock in the frequency range of 40..80MHz (divided by 2 later for ADC clock). AD9952 is used in PLL bypass mode as the complete system must be able todo instant changes to the the frequency (both for AD9952 used as per channel signal as to the AD9912 generating master clock). AD9912 has Microcircuits LFCN-80 low pass filters in the feedback path in series with capacitors. AD9912 output is used as clock to AD9952 directly (with DC block capacitors), final design will use AD9512 clock distribution IC to send the master clock or master clock/2 to all channels and FPGA.

 

To our pleasant surprise the complete system did start to work almost instantly as designed, as soon as we wrote some C code to initialize the programmable devices used, we got output signal!

 

Now question(s):

Having AD9952 clocked at near 80 MHz (78MHz to be exact) and generating 1MHz output signal we see DDS DH2 spur at about -58dB, never better if we look at AD9952 datasheet, then results at about -70dB should be possible, but no matter we do, we have not seen second harmonic (DH2 ?) below 60dB. Is this normal or do we have some design error?

 

What makes us worry a bit is the fact that we measured about same value for DH2 when using AD9952 output directly to AD8251, as when using the two stages low pass filter, the measurement was about the same, but for 1MHz fundamental signal our low pass should have filtered DH2 already. Of course for lower output signals the low pass will not filter DH2 or DH3 an more, so we really depend on the DDS output to be clean enough.

 

In our setup we use only SMA cables between functions blocks and Agilent DS090254A again connected directly to the signals (with resistor divider to adjust the voltage range). DH2 is measured with DSO FFT function. Measuring the signal with spectrum analyzer (Signalhound) did give about same results, DH2 was around -52dB (but we do not trust that much those reading as Signalhound is not that good instrument for low frequency measurements.

 

AD9912 derived clock is also used to drive AD7760 ADC converters, we hope that the clock generated has low enough jitter, but this is very hard to prove until we have actual measurements of the ADC. We are waiting for 0.3ppm THD sinus signal generator - signal analysis on good enough signal would be some sort of indication that the jitter is low enough. We do not have equipment to measure the jitter in sub 10pS range our DSO did show 14.5 pS RMS jitter. Well we do not trust that much this reading from DSO and the measurement was done on single HSTL output from AD9912 connected to DSO (via bypass capacitor of course). Sure for AD7760 clocking we must somewhere convert the differential clock to single ended again.

 

Our test system is currently made from 10 different "building blocks" so we can change some function block to be done using different IC or different schematic-values, so any help at this stage is valuable as we can still change the design.

 

Antti

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