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Enhanced PPI External Synchronization problem

Question asked by alpkrs on Jul 13, 2009
Latest reply on Dec 4, 2009 by asinav

Hi all,

 

We have a project with a basic task to get images from an image sensor to process with a BF548. Since our image sensor board is being designed, to not to waste time waiting for it, I have been trying to get image data from a microcontroller with same clock, frame-sync signals and -some random- image data output.

 

I am -only- able to get image data from EPPI1, in no frame sync mode, when PPI1_CONTROL = 0x0002180C. In summary, this is the EPPI control register mode for GP0FS with "internal" trigger.

 

When I try to use external trigger mode with same settings as above, (GP0FS, external trigger; EPPI1_CONTROL = 0x0012184C ) I get no data, even one pixel. I tried all possible clock and sync (POLC and POLS), DMA watermark and dma-packaging combinations without any success.

 

I also try to get data in GP1FS (EPPI1_CONTROL = 0x0002189C) and GP2FS (EPPI1_CONTROL = 0x0012782C) mode with no success.

 

Following values I used in my code are

 

    EPPI1 Register settings for GP0FS:
PPI1_CONTROL = 0x0012184C

 

    EPPI1 Register settings for GP1FS:
PPI1_CONTROL = 0x0002189C
/* # of pxls per line: EPPI_LINE */
{ ADI_EPPI_CMD_SET_SAMPLES_PER_LINE,          (void *)12 },
/* # of empty pixels/line: EPPI_HDELAY */
{ ADI_EPPI_CMD_SET_HORIZONTAL_DELAY,           (void *)0  },
/* # of active pixels/line: EPPI_HCOUNT */
{ ADI_EPPI_CMD_SET_HORIZONTAL_TX_COUNT,     (void *)12 },

 

    EPPI1 Register settings for GP2FS:
PPI1_CONTROL = 0x0012782C
/* # of pxls per line: EPPI_LINE */
{ ADI_EPPI_CMD_SET_SAMPLES_PER_LINE,          (void *)12 },
/* # of empty pixels/line: EPPI_HDELAY */
{ ADI_EPPI_CMD_SET_HORIZONTAL_DELAY,           (void *)0  },
/* # of active pixels/line: EPPI_HCOUNT */
{ ADI_EPPI_CMD_SET_HORIZONTAL_TX_COUNT,     (void *)12 },

 

/* # of lines per frame: EPPI_FRAME */
{ ADI_EPPI_CMD_SET_LINES_PER_FRAME,           (void *)18 },
/* # of empty lines: EPPI_VDELAY */
{ ADI_EPPI_CMD_SET_VERTICAL_DELAY,              (void *)0  },
/* # of active lines per frame: VCOUNT */
{ ADI_EPPI_CMD_SET_VERTICAL_TX_COUNT,         (void *)18 },

 

respectively.

 


EPPI clock frequency is 100 ms, thus approximately 10Hz.Each cell of logic analyser output is 250ms.


I am using VDSP++ 5.0 and working on ADSP-BF548 EZ-KIT Lite rev 1.4 with silicon rev 2.0. I have disabled keypad and LCD via relative dipswitches. FS3 is pulled down. FS1 is HSYNC and FS2 is VSYNC. Logic analyser output of our sensor-board-emulating-micro is attached. First two pins are clock, others are VSYNC, HSYNC and a start signal I use to trigger microcontroller respectively.

 

I have examined linux kernel source but could not find anything special ( for my case of course :] ). I also looked at anomalies documents. There are many samples in blackfin\examples for video out but I could not find any for video in. So anyone have an idea or suggestion? Has anyone got any experience or working example for EPPI data-in?

 

Thanks in advance

 

Alper

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