For COMIID0 (Table 99) is the higher priority number, 1 or 4? i.e. if both a "Receive buffer full" and "Transmit buffer empty" interrupt are present when COMIID0 is read, irrespective of which occurred first, would COMIID0 be 4 or 2? I'd presume 1 is highest priority, but would like confirmation. Also, clearing of "Transmit buffer empty" is read from COMIID0 (not COMIID) in "Clearing Operation" column of Table 99?.
Any recommendations yet for handling simultaneous RX & TX UART interrupts (see ez.analog.com/thread/9420)? If I read this right the suggestion is that reading COMIID0 may clear the "Transmit buffer empty" interrupt if both a "Receive buffer full" and "Transmit buffer empty" condition are present.
For COMIEN0, ELSI (Table 96), should this be any of COMSTA0[4:1] instead of [3:0].