I use ADC AD7195 with MCLK=5.12MHz, FS=1, SYNC4 filter and I expect Fout=5120000/4/1024=1250Hz output sample rate. But practically I have 1245Hz. Where I can make a mistake?
Thanks in advance.
Attached is an application note which lists the complete equations for settling time and output data rate for the different filter options. From your last reply, you are using ac excitation and you have the chop bit set. When ac excitation is used, chopping is automatically performed. So, it is not necessary to set the chop bit.
From the application note, the output data rate with chop enabled is
fADC = fCLK/(1024 × FS[9:0] × 4 + 16)
= fCLK/(4096 × FS[9:0] + 16)
When the sinc4 filter is used. With a 5.12MHz clock and FS = 1, this gives an output data rate of 1245Hz (see page 5 of AN-1084).
So, you are seeing the correct performance from your AD7195 part.
I would like to confirm whether you are using a single channel or multi-channels? In addition are you using zero latency?
I use single channel mode and not use zero latency (Bit 11 in mode register 0).
Can you please send me the values of your registers? Also, Can you tell me the tolerance of your clock?
The tolerance of your clock can affect your output data rate. For example, if we have a tolerance of +/-1% in our clock of 5.12MHz, we would expect to have a change in our output data rate of about +/-1% resulting to 1262.5Hz/1237.5Hz.
Thanks and best regards,
Mode = 0x040401
Configuration = 0xC01017
Gpocon = 0x40
I use Fluke 164 for measure MCLK , it give out result 5.1199750MHz. I think that 5ppm MCLK error is good value.
Chris, big thanks!
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