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AD7760 - /DRDY pulse width

Question asked by Mr.K on Aug 31, 2012
Latest reply on Sep 24, 2012 by MClifford


I have a question about /DRDY of AD7760.


My device setting is as follows.


・Filterd Output

MCLK = 40MHz

Control Register 2 = 0x0092

     : /CDIV = 0 (ICLK = 1/2 MCLK = 20MHz)

Control Register 1 = 0x001A


In the data sheet, the pulse width of /DRDY is "0.5 × tICLK".

However, the /DRDY pulse width of my circuit is "tICLK(50ns)".


Is this behavior correct though the /DRDY pulse width of my circuit is different from the data sheet description?