AnsweredAssumed Answered

AD9265-FPGA interface at 125 Mhz

Question asked by azs on Aug 29, 2012
Latest reply on Aug 30, 2012 by robwood

Hi all,

I am having problems with the interface between the AD9265 ADC and my FPGA (spartan 6) I am using LVDS in the interface and the clock frequency is 125 Mhz. The CLK for the ADC is an FPGA output. The problem is that sometimes (not always) the input value in the FPGA is not valid.

Does anyone an example of this type of interface??

I am using  IBUFDS and IDDR2 and IBUFDS_DIFF_OUT  for the DCO clock from the ADC.

Any idea?

 

Thanks

 

AZS

Outcomes