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ADF4193 manual bandwidth register setting

Question asked by rmccourt on Aug 28, 2012
Latest reply on Aug 28, 2012 by rbrennan

In the ADF4193 eval board software, there is a setting to lock the PLL into wide bandwidth mode, which was useful for us in debugging some stability issues with an external op-amp. Now that we have the board back, I don't see the register setting that accomplishes that. What is the procedure for manually locking the ADF4193 into wide bandwidth mode?


Thanks -