We are planning to use AD7625 on the next project.
In your datasheet Rev.A|Page 5 of 24, CLK period is up to 3.33ns, but CLK-to-D delay is max 7 ns, typically 4ns.
data delay is larger than clock periold, I think something is wrong. (data io buffer is LVDS,but the delay is too large)
if data delay is correct, how about chaning CLK frequency and period correctly.
it makes me so confused