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When they are really available ADC data in BF506F with ACM?

Question asked by mauri1106 on Aug 27, 2012
Latest reply on Mar 30, 2014 by Prashant

Hi guys, I have a question about effective data availability when I use ACM on BF506F with internal ADC.

I will try to better explain my issue.

I have 2 ACM events synchronized with PWM0_SYNC working at 100kHz: the second one is queued in FIFO so it can be executed immediately after the first.

The communication channel for ADC is SPORT0 (with secondary channel because each event reads 2 different ADC channels) with DMA enable.

DMA receive buffer is 2 "short" deep, the fsclk is 400MHz and the SPORT clock is 25MHz

If each event is enabled separately, all works fine and I'm able to read data from internal ADC in "Event Complete ISR", but when both are enabled there are some confusion between data in DMA buffer in "Event Complete ISR" because it seems that data in the buffer doesn't reflect the event complete sequence.

 

Are there some way to associate DMA buffer content with respective event?

 

Note that I'm forced to read data after every event completes and I can't buffer all data into a 4 "short" deep buffer: this because the next step will be to have a third ACM event synchronized with PWM1 working at variable frequency around 20kHz (both pwm signals are not synchronous with each other, however) so the event sequence is not guaranteed and, maybe, some event could be missed.

Thanks in advance

Maurizio

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