In any system where the FPGA or uP drives the high speed DAC, how to we make sure that all the samples sent out by the FPGA is latched properly by the DAC ie., how thus the FPGA know at what interval the samples must be fed on to the DAC. There are some DACs with Data clock outputs. Some do not have these outputs. In the latter case, how do we maintain synchronization between DAC and FPGA. Should we give common clock to both FPGA and DAC.
Thanks in advance