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ADV7611 (iPhone(720x480p) -> ADV7611 -> BT656(8 bit YCbCr 4:2:2) -> Display(720X480p)

Question asked by coollee on Aug 20, 2012
Latest reply on Aug 23, 2012 by coollee

Hello.

 

I've succeeded to get 720x480p from iPhone by modifying EDID.

But I have some problem.

Horizontal image is ok but vertical image is not right.

1/2 of the original image is only expressed.

This is my REG script.

{0x98, 0x00, 0x0A}, // VID_STD

{0x98, 0x01, 0x05}, // Prim_Mode =101b HDMI-COMP

{0x98, 0x02, 0xF5}, // Auto CSC, YCrCb out, Set op_656 bit

{0x98, 0x03, 0x42}, // 36 bit SDR 444 Mode 0

{0x98, 0x05, 0x28}, // AV Codes Off

{0x98, 0x0B, 0x44}, // Power up part

{0x98, 0x0C, 0x42}, // Power up part

{0x98, 0x14, 0x7F}, // Max Drive Strength

{0x98, 0x15, 0x80}, // Disable Tristate of Pins

{0x98, 0x19, 0x83}, // LLC DLL phase (Matt)

{0x98, 0x33, 0x40}, // LLC DLL enable

{0x44, 0xBA, 0x01}, // Set HDMI FreeRun

{0x64, 0x40, 0x81}, // Disable HDCP 1.1 features

{0x68, 0x9B, 0x03}, // ADI recommended setting

{0x68, 0x00, 0x08}, // Set HDMI Input Port A (BG_MEAS_PORT_SEL = 001b)

{0x68, 0x02, 0x03}, // Enable Ports A & B in background mode

{0x68, 0x83, 0xFC}, // Enable clock terminators for port A & B

{0x68, 0x6F, 0x0C}, // ADI recommended setting

{0x68, 0x85, 0x1F}, // ADI recommended setting

{0x68, 0x87, 0x70}, // ADI recommended setting

{0x68, 0x8D, 0x04}, // LFG Port A

{0x68, 0x8E, 0x1E}, // HFG Port A

{0x68, 0x1A, 0x8A}, // unmute audio

{0x68, 0x57, 0xDA}, // ADI recommended setting

{0x68, 0x58, 0x01}, // ADI recommended setting

{0x68, 0x75, 0x10}, // DDC drive strength

{0x68, 0x90, 0x04}, // LFG Port B

{0x68, 0x91, 0x1E}, // HFG Port B

 

{0x98, 0x03, 0x00}, // 8-bit SDR ITU-656 mode

{0x98, 0x19, 0xC3}, // LLC DLL phase (Matt)

{0x98, 0x04, 0x42}, // OP_CH_SEL

{0x98, 0x05, 0x2C}, // AV code on

 

These are debug information while ADV7611 is in operation.

LLC = 54MHz

[GLB INFO] VID_STD = 10(0x0A)

[GLB INFO] Selected STDI has detected a progressive input

[GLB INFO] CP core is processing the input as a progressive input

[GLB INFO] CP core processing for a progressive standard while Video standard and the INTERLACED bits are configured

              

 

     for an interlaced standard

[GLB INFO] Input is detected as interlaced and the CP is programmed in an interlaced mode via VID_STD[5:0]

[GLB INFO] +5V applied to HPA_A pin by chip

[GLB INFO] No interrupt on INT1

[HDMI_INFO] AVMUTE not set

[HDMI_INFO] HDCP keys and/or KSV HDCP keys read

[HDMI_INFO] HDCP keys read error

[HDMI_INFO] The TMDS PLL is locked to the TMDS clock input to the selected HDMI port.

[HDMI_INFO] The audio DPLL is locked

[HDMI_INFO] HDMI Mode Detected

[HDMI_INFO] The input stream processed by the HDMI core is not HDCP encrypted

[HDMI_INFO] The HSync is active low

[HDMI_INFO] The VSync is active low

[HDMI_INFO] HDMI_PIXEL_REPETITION 1 x

[HDMI_INFO] Vertical filter has locked

[HDMI_INFO] Stereo Audio

[HDMI_INFO] DE regeneration locked to incoming DE

[HDMI_INFO] LINE WIDTH 720

[HDMI_INFO] FIELD 0 HEIGHT 480

[HDMI_INFO] Progressive Input

[HDMI_INFO] 16-bits per channel(not suppoprted)

[HDMI_INFO] FIELD 1 HEIGHT 480

[HDMI_INFO] No HBR audio packet received within the last 10 HSync

[HDMI_INFO] No DST packet received within the last 10 HSync

[HDMI_INFO] No DSD packet received within the last 10 HSync

[HDMI_INFO] L_PCM or IEC 61937 compressed audio sample packet received within the last 10 HSyncs

[HDMI_INFO] No DST double data rate audio detected

[HDMI_INFO] Video FIFO is locked

[HDMI_INFO] FIFO has some margin

[HDMI_INFO] TOTAL LINE WIDTH 858

[HDMI_INFO] HSYNC FRONT PORCH 16

[HDMI_INFO] HSYNC PULSE WIDTH 62

[HDMI_INFO] HSYNC BACK PORCH 60

[HDMI_INFO] FIELD 0 TOTAL HEIGHT 1050

[HDMI_INFO] FIELD 1 TOTAL HEIGHT 1050

[HDMI_INFO] FIELD 0 VS_FRONT_PORCH 18

[HDMI_INFO] FIELD 1 VS_FRONT_PORCH 18

[HDMI_INFO] FIELD 0 VS_PULSE_WIDTH 12

[HDMI_INFO] FIELD 1 VS_PULSE_WIDTH 12

[HDMI_INFO] FIELD 0 VS_BACK_PORCH 60

[HDMI_INFO] FIELD 1 VS_BACK_PORCH 60

[HDMI_INFO] CS_DATA[4] 4

[HDMI_INFO] CS_DATA[3] 1

[HDMI_INFO] CS_DATA[2] 0

[HDMI_INFO] CS_DATA[1] 2

[HDMI_INFO] CS_DATA[0] 219

[HDMI_INFO] TMDSFREQ 80

[HDMI_INFO] TMDSFREQ_FRAC 115

[HDMI_INFO] YUV_709

[HDMI_INFO] CTS 27027

[HDMI_INFO] N 6144

[REPEATER_INFO] Flags internal EDID Enabled

[INFOFRAME] AVI version 2

[INFOFRAME] AVI length 13

[INFOFRAME] Audio version 1

[INFOFRAME] Audio  ength 10

[INFOFRAME] Source Prod version 0

[INFOFRAME] Source Prod length 0

[INFOFRAME] MPEG Source version 0

[INFOFRAME] MPEG Source length 0

[INFOFRAME] Vendor Specific version 0

[INFOFRAME] Vendor Specific length 0

[INFOFRAME] ACP version 0

[INFOFRAME] ACP length 0

[INFOFRAME] ISRC1 version 0

[INFOFRAME] ISRC1 length 0

[INFOFRAME] ISRC2 version 0

[INFOFRAME] ISRC2 length 0

[INFOFRAME] Gamut version 0

[INFOFRAME] Gamut length 0

[CP_INFO] Sync channel 1 STDI measurement are valid

[CP_INFO] Indicates a video signal on sync channel 1 with non interlaced timing

[CP_INFO] CH1_BL(Block Length) 2421

[CP_INFO] CH1_LCF(Line Count) 524

[CP_INFO] CH1_LCVS(Line Count in a VSyn) 6

[CP_INFO] CH1_FCL(Field Count Length) 622

[CP_INFO] The parameter buffering block has lock to the synchronization signal from the HDMI core

[CP_INFO] The timing buffer filter has locked to the HDMI input

[CP_INFO] CSC is bypassed

[CP_INFO] The CP is not free running

 

Please help me.

P/S. I found below at the other discussion.

·         1) BT656 will work for 480i, 576i normally 27MHz.

     I got some results also for 480p, 576p (which will be 54 MHz),

     however these are a little nonstandard and may need some additional tweaking.

Outcomes