I'm operating the AD7626 in self-clocked mode at 10 MSPS. The digital host is a Cyclone 4 FPGA, the board is customer specific.
Right now I have a problem receiving the sequence bits "010" on the LVDS data lines.
What I have managed so far: The ADC is reacting to CNV rising edge and also to CLK bursts (18 cycles). I verified this on scope and also with Altera Signal Tap LA (data is matching). When I do not issue clock or CNV the data line is low, which should be ok.
When sending a CNV pulse to the ADC with 18 clock bursts the data line is changing, but I don't get the start sequence "010". When analyzing the data with the logic analyzer it seems, that the data bits are changing according to the inputs, which is also ok, unless the sequence bits are missing.
I double checked, that DCO+ is grounded, DCO- is currently left floating à must it also be grounded?
What will happen when I issue 18 CLK cycles simultaneously with the very first CNV rising edge? Should I get invalid data with correct sequence bits or will it produce senseless data?
PS: I just tried to set the CLK to IDLE LOW during the Quiet phase (verified the LVDS signals with scope) and now I'm receiving a valid start sequence. Did I read something. over?
Thanks in advance,