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AD9957 PDCLK output pin "collapsing" above 80MHz

Question asked by Ratch on Aug 20, 2012
Latest reply on Aug 20, 2012 by KennyG

     We have an application where we are running the AD9957 chip at 960MHz(RefClk) and are generating a PDCLK rate of 160MHz with a CCI interpolation rate = 3.  The chip is being operated in Quadrature Modulation mode with an I-Q sampling rate of 80MHz. In this configuration the I and Q data samples are clocked into the device in an interleaved fashion on the rising edge of PDCLK.  When we view the PDCLK output pin of the AD9957 chip on an Oscilloscope the signal looks very poor at higher frequencies.  The expectation was a square clock signal with 50% duty and near constant amplitude swing for different PDCLK values within the 250MHz max. limit.  What we see in the actual application is that PDCLK values < 80 MHz look as expected but >= 80MHz PDCLK values deterioriate in quality as the PDCLK increases to our desired value of 160MHz.  At a PDCLK value of 160MHz the amplitude swing of PDCLK output decreases considerable, the duty cycle is no longer 50%, and the clock is no longer "clean".  We run the PDCLK output of the AD9957 chip into an FPGA PLL which cleans up the clock and this signal is used to clock I-Q samples into the AD9957 device.  Although the documentation for the AD9957 device indicates a PDCLK max frequency of 250MHz is there a limitation or design considerations which must be accounted for on the single ended PDCLK output pin 40 of the device which we are using to develop a clock for input clock synchronization of I-Q samples into the modulator.