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AD9963 datasheet errata?

Question asked by murphpo on Aug 19, 2012
Latest reply on Aug 20, 2012 by larrywelchusa

I'm working with a board with the AD9963. In debugging our designs, I've observed some behaviors different from those described in the "Rev. 0" datasheet.

 

I believe AD9963's interpretation of the following register bits is inverted from the datasheet descriptions. I've observed the following behaviors in hardware:

  • 0x31[0]: TX_BNRY; setting this to 1 configures the DACs to interpret samples as two's complement
  • 0x32[0]: RX_BNRY; setting this to 1 configures the ADCs to output two's complement samples
  • 0x51[4]: RX_PTTRN; setting this to 1 drives the checkboard pattern to TRXD
  • 0x75[3]: DLL_RESB; if this bit is 1, the DLL never locks. If it's 0 (i.e. I treat the reset as active-high), the DLL works as expected.

I've observed odd I/Q DAC behavior when changing RSET_SEL (reg 0x62[0]). When RSET_SEL=1, the full scale current of the I and Q DAC outputs rises very slowly, increasing by >1mA in ~3 minutes.

 

Our board has a 10k/1% resistor to ground at pin 6 (RXBIAS) and a 0.1uF X5R cap to ground at pin 63 (REFIO).

 

A few observations:

  • If I leave RSET_SEL=1 for a few minutes and let the full scale current rise, then set RSET_SEL=0, the full scale current resets to its nominal level and remains constant.
  • If I leave RSET_SEL=1 for a few minutes and let the full scale current rise, then set RSET_SEL=0, then set RSET_SEL=1, the full scale current briefly resets to its nominal level (while RSET_SEL=0), then starts rising again, starting over from its nominal level.
  • I also measured the voltage at REFIO (pin 63) during these tests. When RSET_SEL=0, V_REFIO=1.0V; when RSET_SEL=1, V_REFIO=~20mV.
  • I see the same behavior at REFIO when changing TXDAC_PD reg 0x60[6]; when TXDAC_PD=1, REFIO=~20mV; when TXDAC_PD=0, REFIO = 1.0V.
  • However when TXDAC_PD=1, the I/Q DAC full scale current drops to ~0.1mA (or something similarly low; this is hard to measure with my equipment).

 

Is the DAC voltage reference somehow dependent on RSET_SEL, in addition to TXDAC_PD?


Datasheet typos:

 

  • Fig. 70: the label for the N block says "M[3:0]"
  • Pg. 36: the decimation filter stopband rejection is described as 7dB (should be 70dB?)

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