I have setup an ADAU1761 to work with a digital microphone ADMP421. The microphone input signal works fine and I can route it to the serial port or the SigmaDSP processing unit. However, I am still wondering about the following note in the codec manual. At page 66, in the description of the bit INSEL in register R19, it says:
"Digital microphone input select. When asserted, the on-chip ADCs are off, BCLK is master at 128 × f_S, and ADC_SDATA is expected to have left and right channels interleaved."
What is the meaning of "128 × f_S" for BCLK?
I have setup the codec for a base sampling frequency of 48.0 kHz and a sampling frequency of 16 kHz (ADC and DAC, DSP and serial port), the serial port is configured for 64 bit clock cycles per frame. At BCLK I measure a clock frequency of 1024 kHz, which is neither 128 * 48 kHz nor 128 * 16 kHz. When I set the serial interface to 128 clock cycles per frame, then there is no more input signal from the microphone (i.e. only a zero signal).
Can anyone resolve this discrepancy?