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BF592 SPI DMA anomaly on direction change

Question asked by Scott.Wagner on Aug 16, 2012
Latest reply on Aug 26, 2012 by Scott.Wagner



On BF592A design, I am using SPI1 in slave mode with DMA in the following context:

1) Receive (using TIMOD=b10) a message of 1 or more bytes

2) Process the message and generate a return message.  Reprogram the SPI (and DMA) to TIMOD=b11

3) Wait for master to read out the response.


This works fine most of the time.  However, occasionally (perhaps 5 - 10% of transfers) a "rogue" byte leads the response in the SPI MISO data coming from the BF592.  This byte is always the last byte received by the SPI subsystem on the MOSI signal.  That is, it seems that the last byte received occasionally gets "stuck" somewhere (the DMA FIFO?) and is reemitted as the first transmitted byte of the response message.


When this happens, the BF592 will have successfully read that last byte of data in the incoming message.


I have verified that the last byte is NOT the first byte in the DMA buffer I am transmitting, even when it appears on the MISO signal.


Please note that this is sporadic behavior - it does NOT happen on every transfer, and as far as I can tell all system timing is the same whether the anomaly occurs or not.


Any ideas?  Need more info / code samples?  Thanks!