AnsweredAssumed Answered

ADF4106 Digital lock detect problem

Question asked by Devilfrog on Aug 15, 2012
Latest reply on Aug 16, 2012 by rbrennan

My pll setting value:


Fout: 1 Ghz
Reference frequency: 100MHz


Register setting value :

  1. Reference counter Latch Map – 0x000010
  2. AB Counter Latch Map – 0x000501
  3. Function Latch Map – 0x1F8092
  4. Initialization Latch Map – 0x1F8093


When unlock situation, digital lock detcet out isn't stay low state. It looks like pulse signal. but it doesn't have uniform period. It shows up high and low repeatedly.

1. No reference: repeat high and low state

2. No loop filter: repeat hign and low state

3. No RF: low state


What is the solution of this problem?