My pll setting value:
Fout: 1 Ghz
Reference frequency: 100MHz
Register setting value :
- Reference counter Latch Map – 0x000010
- AB Counter Latch Map – 0x000501
- Function Latch Map – 0x1F8092
- Initialization Latch Map – 0x1F8093
When unlock situation, digital lock detcet out isn't stay low state. It looks like pulse signal. but it doesn't have uniform period. It shows up high and low repeatedly.
1. No reference: repeat high and low state
2. No loop filter: repeat hign and low state
3. No RF: low state
What is the solution of this problem?