The data sheet says about Rsel# pin :
"Range Select Pin. Tying this pin to DGND selects a DAC output range of 0
V to 60 V, alternatively tying R_SEL to VLOGIC selects a DAC output range of 0
V to 30 V."
Is it possible to connect Rsel# to an FPGA without PU or PD, so the FPGA
controls the range.
The DAC is powered first and the FPGA is configured after, so the pin is not
defined when the FPGA is powered.