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AD5504 - Rsel pin

Question asked by Shahar on Aug 12, 2012
Latest reply on Aug 21, 2012 by KenK

Hello

The data sheet says about Rsel# pin :

"Range Select Pin. Tying this pin to DGND selects a DAC output range of 0

V to 60 V, alternatively tying R_SEL to VLOGIC selects a DAC output range of 0

V to 30 V."

Is it possible to connect Rsel# to an FPGA without PU or PD, so the FPGA

controls the range.

The DAC is powered first and the FPGA is configured after, so the pin is not

defined when the FPGA is powered.

Thanks

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