I have board with 5V coming in which is dropped to 3.3V by an LDO linear voltage regulator. The board has an FPGA with a 3.3V LVTTL 16-bit data bus and drivers for an AD5547 and AD7606-4. The AD5547 uses Vdd=5V. The AD7606-4 uses Vcc=5V and Vdrive=3.3V. Nothing else that the FPGA drives uses 5V. The AD5547 has a +10V reference and is connected as two four-quadrant multiplying DAC's. So far I have not attempted to drive or read anything with the data bus.
The problem is that output of the 3.3V regulator is pulled up to 3.6V which is over the FPGA's recommended maximum operating voltage. I can get it down to 3.3V by loading it with about 100 ohms or less to ground, so the regulator can control the voltage. This appears to be backdriving by the AD7606-4 or the AD5547. Is it normal?