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Timing on AD9880 outputs

Question asked by Blackbird on Aug 9, 2012
Latest reply on Aug 14, 2012 by GuenterL



The AD9880 (Device) datasheet specifies:

Table 1 : data to clock skew is -0.5ns to +2.0ns.

Table 2 : clock to data skew is -0.5ns to +2.0ns.


I think the data in the two tables is confusing and contradicitng:

If data-clock, and also clock-data skews can both be +2.0ns in worst case,

then it seems that :

1. The -0.5ns datum is irrelevant and redundant.

2. tCO (time from clock falling, to valid data at output) may vary from -2.0ns to +2.0ns.


I guess the datasheet's author really meant to say that

the delay from clock fall until data becomes valid could be 2.0ns max., however, in some

Devices the data can also be 0.5ns earlier relative to clock fall.

But I'm not sure that this is what the author meant, since the datasheet is not very clear on this matter.


I would like to ask:

1. When does the -0.5ns datum play a role ?

2. What is the actual tCO of the device ? (Time from CLOCK fall to OUTPUT data valid)


I am asking this, because currently I assume tCO= -/+2ns, and this makes it difficult for my FPGA to meet timing constraints

(input setup, and input hold times) while working in 1080p (pixel clock of 148.5MHz).