I am trying to use Ex-Clk (48MHz) as the PCG source clock to generate ADC control signal.
Here I want to use 4xEx-Clk as ADC's SCLK, so I set CLKADIV=0x00000004 (the Tsclk=4x (1/48 MHz)= 4 x 20.8 nS=83 nS).
I use 18-Bit ADC (AD7982), and I use 31 SCLKs (31 x4=124 Ex-clk= 0x7C) as FS, so I set FSADIV=0x0000007C (Tfs=124 x 20.8=2.58 uS); And the Converter time uses 13 SCLKs (13 x 4=52 Ex-Clk=0x34), so I set PWFSA=0x00000034; (the rest 18 SCLKs for ADC data transfer).
When I ran the code, and measured the period of the SCLK and FS, I found only the Tsclk was correct (about 84 nS), but Tfs was only 1.24uS, and I got only 9 SCLKs for the data transfer but not 18.
Followed diagrams the periods of the SCLK (84 nS) the yellow trace and FS (1.24 uS) the blue trace.
Maybe I got something problem at the PCG setting. Would you please check the attached code to see what's wrong with the setting?