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Clock signal delays in TDM, how to handle

Question asked by Hfuhrhurr on Aug 7, 2012
Latest reply on Aug 27, 2012 by jeyanthi.jegadeesan

Hi all,

 

we have a design problem with an ADSP21469 on a mainboard and an ADC on a separate board which is galvanically isolated by an ADuM 1280.

The problem is that the ADuM (C grade) causes a delay of max 24 ns and we'd like to use 48kHz 8 channel TDM with a bitclock of 12.288 MHz with a cycle of about 81.4 ns.

The clock is generated by the DSP and passed via the ADuM to the ADC. The data from the ADC is passed via the ADuM to the DSP.

So, there is a 48ns delay of the data at the DSP caused by the ADuM + 10 ns SDOUT output delay due to the ADC.

From the datasheet of the ADSP21469, I can see that there is a timing requirement of 7ns data setup before the sampling edge at the receiving SPORT.

So, we have a delay of 24+24+10 ns = 58ns between BCLK at the receiving SPORT and incoming data. We need to be there at 81.4-7ns = 74.4 ns.

 

Should work. Did I overlook something?

 

Best regards,

 

Rainer

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