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ADuC702x Data Sheet Rev E, 07/2012 & F, 05/2013

Question asked by ADUzer on Aug 3, 2012
Latest reply on Aug 21, 2012 by MMA

Outstanding errors in ADuC702x Data Sheet Rev F, 05/2013

 

  • GP3PAR not documented (ez.analog.com/message/74631). In Keil header files. Appears to have default value of 0x00222222.
  • Information in Table 84 (GPxPAR) seems to contradict info in  ez.analog.com/thread/3960 which says "Note that the drive strength is only configurable on the following port pins: P0.7, P3[5-0]". See http://ez.analog.com/thread/34087
  • No change to t(dav) in Table 7 (http://ez.analog.com/thread/11055)
  • Rev E data sheet changes bit 6 in table 18 from enable ADC_BUSY to Reserved. Description of ADCSTA on page 48 still says "This information can be available on P0.5 (see the General-Purpose Input/Output section) if enabled in the ADCCON register.". Should be "This information can be available on P0.3 and/or P0.5 (see the General-Purpose Input/Output section).".
  • Page 88 for Timer 3 (watchdog) says "..The clock source is 32 kHz from the PLL..". The text is not clear that this excludes the external crystal (which can also drive the PLL). Figure 67 shows that only the (+/- 3%) internal oscillator can be the source for Timer 3.
  • Page 71, "Normal 450 UART Baud Rate Generation". Denominator says "2^CD - 16 × 2 × DL". Should be "2^CD × 16 × 2 × DL", as in Rev D data sheet.
  • Page 11. Is note 3 for Table 1; "Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN)." relevant to the parameter "Logic Inputs", and possibly others?
  • Page 72, Table 103. For DLAB, should say "....enable access to COMRX, COMTX and COMIEN0."
  • No mention of PLLSTA MMR in data sheet. Initially acknowledged in July 2010 when Rev C data sheet was current, (http://ez.analog.com/thread/3995). In Keil header files. Information on MMR was removed but subsequently re-referenced : http://ez.analog.com/thread/19630.
  • Potential undocumented interrupt issue (silicon anomaly?) with duplex UART communications. (http://ez.analog.com/thread/17515).
  • 9 characters in addresses for external memory region 3, 2, 1, 0 on Figure 35. Rev F, page 41.
  • Configuring P1.7 as chip select in the serial port mux, when the SPI interface is configured in master mode with CS output enabled, disables/resets the SPI configuration. Silicon anomaly? See http://ez.analog.com/thread/11060
  • Page 53, FEEADR. Says "FEEADR is another 16-bit address register.". It is the only address register. Maybe there is a FEEADRL and FEEADRH on other devices as address 0xF814 is not assigned a use in the MMR list.

 

ADuC702x Data Sheet Rev E, 07/2012

 

  • No mention of drive strength in Table 82 (http://ez.analog.com/thread/3960?tstart=0)
  • GP3PAR not documented (ez.analog.com/message/74631). In Keil header files. Appears to have default value of 0x00222222.
  • No change to t(dav) in Table 7 (http://ez.analog.com/thread/11055)
  • Rev E data sheet changes bit 6 in table 18 from enable ADC_BUSY to Reserved. Description of ADCSTA on page 44 still says "This information can be available on P0.5 (see the General-Purpose Input/Output section) if enabled in the ADCCON register.". Should be "This information can be available on P0.3 and/or P0.5 (see the General-Purpose Input/Output section).".
  • Page 82 says "Timer2 can be used to start ADC conversions as shown in the block diagram in Figure 67." Figure 67 does not show this. Timer 2 cannot initiate and ADC.
  • Page 83 for Timer 3 (watchdog) says "..The clock source is 32 kHz from the PLL..". The text is not clear that this excludes the external crystal (which can also drive the PLL). Figure 57 shows that only the (+/- 3%) internal oscillator can be the source for Timer 3.
  • Page 66, "Normal 450 UART Baud Rate Generation". Denominator says "2^CD - 16 × 2 × DL". Should be "2^CD × 16 × 2 × DL", as in Rev D data sheet.
  • Page 67. Clearing of "Transmit buffer empty" is read from COMIID0 (not COMIID) in "Clearing Operation" column of Table 99.
  • Page 66. For COMIEN0, ELSI (Table 96), should be any of COMSTA0[4:1] instead of [3:0].
  • Pages 7 & 8. Is note 3 for Table 1; "Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN)." relevant to the parameters  "Glitch immunity on reset pin", "Logic Inputs", and possibly others?
  • Page 67, Table 101. For DLAB, should say "....enable access to COMRX, COMTX and COMIEN0."
  • No mention of PLLSTA MMR in data sheet. Initially acknowledged in July 2010 when Rev C data sheet was current, (http://ez.analog.com/thread/3995). In Keil header files.
  • Potential undocumented interrupt issue (silicon anomaly?) with duplex UART communications. (http://ez.analog.com/thread/17515).
  • 9 characters in addresses for external memory region 3, 2, 1, 0 on Figure 35. Rev E, page 37.
  • Configuring P1.7 as chip select in the serial port mux, when the SPI interface is configured in master mode with CS output enabled, disables/resets the SPI configuration. Silicon anomaly? See http://ez.analog.com/thread/11060

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