For the AD9858 and AD9914 chips, when I apply a reset signal, is there then definite time delay between one edge of RESET, and subsequent edges of SYNC_CLK? Are these delays specified anywhere?
Of course I am applying REF_CLK all the while.
When the master reset is at a logic high state, the SYNC_CLK signal on the SYNC_CLK pin should go low and remain low unitl the master reset is released. When the master reset signal goes back to a logic low state, the SYNC_CLK should start to toggling again. Unfortunately, that time was not characterized but whatever it is should be consistent ( +/- an SYNC_CLK period or two) across parts for a given product. Hope this helps.
That helps, but I was hoping for a tighter constraint. My goal is similar to what you describe in this post:
but my requirements for multi-chip sync are less stringent. I just want to synchronize one programming source to multiple DDS with as little overhead as possible.
The aim is to synchronize FPGA programming signals to SYNC_CLK in this way. If the time delay between the falling edge of RESET and the rising edge of SYNC_CLK was consistent to 1 ns or so, this would allow me to meet timing requirements for subsequent UPDATE signals vs. SYNC_CLK.
My FPGA clock is derived from the same source as REF_CLK, and the FPGA frequency has an integer relationship to the SYNC_CLK frequency, so it seems like RESET could be used to establish a consistent timing relationship between FPGA and DDS. Then the FPGA output timing can be fine tuned to meet setup and hold requirements for UPDATE vs SYNC_CLK.
But if timing fluctuations are greater than 1 ns or so, it may be necessary to tune the FPGA delays every time the DDS is reset. This is possible but less convenient.
FYI, I have measured the delay between RESET (falling edge) and SYNC_CLK on one AD9858 chip when REF_CLK is 1 GHz. In twenty measurements the minimum was 137 ns, and the maximum was 139 ns, not accounting for cable delays. Some of the jitter may be due to the 7 ns fall time of my RESET signal (2V to 0.8 V). The fluctuations correspond to +/- one REF_CLK cycle.
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