Please advise to me!
We evaluate the AD7760.
Input the CLK "MCLK = 39.66MHz".
After power-up sequence, set the control register 2,1.
Holds the set to " / CDIV = 1" (MCLK = ICLK).
to different settings, change the control register when 2,1,
Register will be changed as follows.
"/ CDIV = 1 (MCLK = ICLK)" ⇒ "/ CDIV = 0 (MCLK / 2 = ICLK)"
Is this correct behavior?
Then understood as follows.
Power-up sequence (reset?) is only once.
"On power-up, the default is ICLK = MCLK/2 to ensure that the part can handle the maximum MCLK frequency of 40 MHz."
The following description is, What is your relation?
datasheet page 33
"Recommended register setting for power-up and normal operation using clock divide-by-2 (CDIV = 0) mode: 0x0002"
このメッセージは次により編集されています: satoshi sasaki Additional questions. When using normal mode, If I set the register to "(/ CDIV = 1) MCLK = ICLK", Are there any problems?