I just have a quick timing question on the BF548's SDRAM timing.
In Memory Control Register 0 (EBIU_DDRCTL0), the tREF (Refresh Interval) is set here. It is said that to obtain this I should take the DDR refresh period (tREF), divide this by the total number of rows to be refreshed, then divide this by the total time.
The only thing I'm uncertain of is what is "total time"? For my system I have a 126 MHz clk for the BF548, a tREF = 64 ms, and 8192 total rows. The only thing that I don't know of is what I asked before. Thanks and I hope to hear back soon.