In single link mode, (referred to as the third output mode) both converters are output on
one link using two lanes and only DSYNCA. After conversion to 8b/10b and optional
scrambling, are the MSBs (bit19) of both converters output first, followed by the next
most MSB,and so on down to bit zero?
This seems identical to the first mode, with the exception of one DSYNC being used
instead of two. Is that right?
Does ADI have a simulation model for the digital output part of the converter?