I have a question on the "manual timing optimization" feature. In my system DATACLK is not used, the FPGA adjusts the input data timing. I wish to use the timing violation interrupt to allow the system to check that timing is correct. In the system the FPGA is configured first, followed by the DAC, but at the point the DAC is configured the data inputs are not changing. I've tried experimenting with the margin and adjusting the input timing and I can see interrupts occurring when the timing is incorrect but I can't seem to get the interrupt to clear reliably - I seem to have to back off the timing a long way for the interrupt to disappear, and even then it doesn't always seem to clear.
My questions are: I've noticed in the datasheet that "One error check operation is performed per device configuration". What is the event that causes this check to initiated (which register write etc)? Is there a way I can defer this single check until data is being sent to the DAC? Better still, is there a way to initiate a check without having to reset and re-configure the DAC?
Also, I notice that register 3 bit 6 is "Reserved, set to 1", but the default value for this register is 0. I have set this bit to zero in previous designs, is the setting of this bit important?