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Regarding AD7766 interface

Question asked by mik22 on Jul 26, 2012
Latest reply on Aug 6, 2012 by mik22

Hello,

I have a problem when reading data from AD7766. I have four of ADC in daisy chain. Data is read by Blackfin processor ADSP-BF518 via SPORT configured in multichannel mode. I'm using the AD7766 read mode when CS signal is constantly low and SCLK is continuous.

According to the documentation, ADC starts to shift out valid data after falling edge of DRDY impulse. When DRDY signal is high data is invalid regardless of SCLK. The problem is that if SCLK is high comparing to DRDY length (in my case 6,25MHz) and therefore there are few SCLK cycles during DRDY pulse, ADC starts to shift out valid data right after rising edge of DRDY . So, this is a problem itself, but what is much worse is that behavior like this is not constant, I mean the beginning of valid data varies from start to start. Once it's started ok, it is stable. But there is no guarantee that the next time it will start ok too. So, is there any established behavior and what does it depend on? I would appreciate if you gave me an advice on how to deal with that.

 

Thanks in advance.

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