I'm new to using the JESD204 ADC interface. I cannot find any timing specifications relative to
DSYNC+/- for the AD9644. I know that SYNC is synchronous to the clock, but does DSYNC+/-
need to be synchronized to the AD9644 clock?
Yes, your clocking scheme sounds like it should work fine. I should have been more clear in my statement. By using the same logic interface what I meant was if using LVDS for the clock it is best to use LVDS for the DSYNC inputs. I hope this clears up any concern you have.
There are not specific timing specifications given since it is specified to assert the DSYNC+/- inputs for at least two clock cycles. DSYNC should be synchronous to the AD9644 clock. It is also recommended for the DSYNC signal to have the same logic interface as the clock in order to achieve reliable timing. For the AD9644, the clock input serves also as the frame clock for the JESD204A interface. If using the M=2, L=2 mode then each channel has its own DSYNC input. If using the M=2, L=1 mode then DSYNCA is used. The DSYNCA/B pins on the AD9644 perform the function specified by SYNC~in the JESD204A specification.
Hope this helps,
Thanks very much Jon. That helps clear things up. I did just find in the 204A spec (in 126.96.36.199) where
~SYNC is sync to the rising edge of frame clock.
Your statement, "It is also recommended for the DSYNC signal to have the same logic interface as
the clock in order to achieve reliable timing." worries me.
I will be driving the AD9644 from a AD9520 and DSYNCA+/- from a FPGA. Both will be differential signals. If the FPGA DSYNCA+/- output is clocked by an internally generated FPGA clock that is synchronous to the external frame clock, things should be OK, right?
Thanks. That is perfect.
Great! I am happy to help out.
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