Our customer made a question about ADuM1400 in their prototype board, which VDD2 is unpowered a little while(maybe around 10ms) during power regulator starting-up to 3.3V triggered by a power switch, against 5V VDD1 is always powered, however there must be no signal transmission until VDD2 becomes stable. Subject to Table 15.Truth Table on page 21 of its datasheet, this unpowered state on VDD2 may not cause any problem, I guess, but is this correct ? Please confirm.
They are experiencing unexpected behavior when toggling the power switch, sometimes they could find VDD1 looks consuming more than 150mA, despite normally 2~3mA, then the regulator activate limiter to depress its' output voltage. They are now checking and considering to their own circuitry and requested to confirm above at the beginning.
Thank you very much for your support and I would appreciate very much for any of your advice.