We are trying to use the DDS chip to:
- generate 50% duty cycle square clocks from 100kHz to 3MHz in 1Hz resolution.
The AD9833 chip is clocked with 25MHz TCXO and we use the MSB output to get the required square wave.
The problem we encountered is that the output frequency and duty cycle cannot stay stable.
1. Set frequency = 1MHz, output = 1MHz but duty cycle flip flops between 50% to 45%
2. Set frequency = 1.1MHz output = 1.135MHz for 1 time, and 1.087MHz for 6 times (attached screen shot)
The frequency register is written only once for a particular required frequency output.
What is actually causing this kind of problem ?
Is there a solution to this problem ?
Can the selection for a longer tuning word width/resolution, say 48bits/14bits, resolve the problem.