I'm using the AD9956_VCO/PCBZ evaluation board. I'd like to disable as many unnecessary subsystems as possible as to increase spectral purity. I'd like to disable the RF divider as my input clock is 100 MHz. If I'm reading the datasheet correctly, this would mean setting CRF2<23> to 1. The description is:
CRF2<23> = 1. RF divider is powered down and an alternate path between the REFCLK inputs and SYSCLK is enabled.
What confuses me is the wording "is enabled". Is it automatically enabled? Or must I also set CRF2<16> (RF Divider SYSCLK Mux Bit) to 1.
I can't get the DDS to work when I set both of these bits to 1. I'm not sure why and any help understanding would be greatly appreciated!
The other question I have is, what is the proper way to disable the DDS output? Currently, I'm using CRF2<39>, the DAC Power-Down Bit, to turn the output on and off. I'm wondering if this is the correct way to do it.
What is bothering me is that when I use this method, I still see a peak at at the same frequency when I turn it off. The peak is about 40 dB lower. What could be causing this? For reference, I'll attach a few screenshots, showing both before and after I power down the DAC. I'm currently operating with the RF divider enabled and set to 1 as I can't see output when I disable it.
Output on: (AL = -5 dBm)
DAC Power-Down: (AL = -5 dBm)
DAC Power-Down: (AL = -60 dBm)
As you can see there is a clearly still some signal there even with the DAC powered down. That signal goes away when I turn off the DDS. It also does not appear until I set the CRF2 register of the DDS. (I first set CRF1.)
I'm setting CRF1 to 0x00004010 and CRF2 to 0x0000180010