How is the 24-bit code signature calculated in the FEESIGN MMR of an ADuC7024?
The flash controller signature command generates a 24-bit LFSR signature.
It automatically reads the entire content of the memory, including the on-chip kernel to generate a unique 24-bit signature in the FEESIG register.
Because the on-chip kernel is read-protected, user code cannot apply the corresponding algorithm to obtain this unique number.
Ok, so the LFSR can't be calculated at run time because the kernel can't be read and also location 0x8F7FF can't be read because of errata er022.
The only way to use the signature would be to embed it at build time, which could only then be used at run time if the flash is not rewritten and the kernel is never revised in the device as time goes by (in case of flash upgrades to parts).
What is / was the anticipated use of FEESIG?
The intended use was to trace code revision or verify flash content.
Because the on-chip kernel is different from part to part (different trimming values are stored in the kernel space), the signature of the same user code can be different from part to part.
Retrieving data ...