Parallel read operation lists /CS to /RD setup time t8 as 0 ns minimum, implying that /CS must not fall after /RD falls. May /RD fall first, so the invalid data shown in Figure 4 during t8 does not appear and t26 starts at the falling edge of /CS?
The /CS signal is used to enable the data lines on the AD7606. T8 being 0 implies that /CS and /RD can go low simultaneously. Driving /CS and /RD simultaneously this will eliminate also the invalid data you mentioned. However the /CS signal must go low prior to or simultaneously with /RD.
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