I am using a ADF4001 PLL block along with a Vectron VCXO to build a classical Phase Modulator around a 2.048 MHz clock. Both R and N registers are set for unity. Finally got the input levels (0 dBm @ 50 OHMS on RFINA) and full 3.3VDC CMOS squarewave level on REFIN. Got phase lock with the following topology:
By varying the Vcmd voltage (from a 16-bit DAC), I should be able to perform phase modulation around the 0 degree phase difference, but get cycle slipping (jump) from some phase modulation say around +/- 20 degrees to 180 degrees out of phase jump but still locked! Also getting severe nonlinearity toward the extremes of the voltage drive from the DAC (+/- 10VDC) where the output phase starts to mnove very fast for smaller and smaller input DAC voltage. No lock break though...
I thought I should get a very smooth phase modulation from DC to about 10KHz (modeled from both ADIsimPLL and ADS2009) simulations. over a +/- 90 degrees about the zero phase differential point at lock and under lock at all times without the cycle slipping.
I also noticed this PFD has a periodic transfer as opposed to an aperiodic transfer which would prohibit me from getting a cycle "jump" to another periodic phase.
Let me know what I am doing wrong with this application of the classic phase modulator.