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AD9522-0 Locking to Incorrect Frequency

Question asked by qgm on Jul 17, 2012
Latest reply on Jul 17, 2012 by pkern

I'm trying to configure the AD9522 in the "Mode 0: Internal VCO and Clock Distribution." On the REFIN input, I have a 12.5 MHz 3.3V CMOS square wave. REFINB has been shorted to ground with a 100 nF capacitor. I have enabled the clock doubler (R0x01D = 0xA0) and set the R divider to 1. For the internal VCO, I have set the P, P+1 prescaler to dual modulus mode, divide-by-32 and divide-by-33 when A != 0 (R0x16=0x06), A = 6 (R0x013 = 0x06), and B = 3 (R0x014 = 0x03). This should result in a total N division of N = (32 * 3) + 6 = 102. Hence, a 2.55 GHz VCO signal will be divided down to 25 MHz, matching what comes on the input side after the clock doubling.

 

For the clock outputs, I have set the VCO divider to 6 (R0x1E0 = 0x04) and set the channel divider Dx = 17 = (10+1) + (5+1) = 17 (R0x190 = 0xA5). Hence, the 2.55 GHz should be divided down by 6 * 17 = 102, so I should get 25 MHz at the CMOS output.

 

I allow the VCO calibration to proceed for 4500*8 clock cycles and have set the VCO calibration divider to 8 (R0x018=0x74) as well as put in the most stringent DLD settings. I monitor using the LD pin the value of (DLD) AND (status of selected reference) AND (status of VCO) (R0x01A = 42) and the pin measures a constant 3.3 V on my scope at the time I'm measuring the frequency of OUT0, leading me to believe the PLL is locked. I don't have the ability to read the registry, only the ability to write to the registry. I think all of this should be enough to give me 25.0 MHz at OUT0. Instead, I'm consistently measuring around 24.3 MHz.

 

Things I have tried:

1) turning on and off duty-cycle correction and going to a more even duty cycle (M = 8 and N = 7).

2) turning on the internal zero delay function (this increases the frequency to around 26 MHz)

3) increasing the number of cycles I allow for VCO calibration (even though the DLD already shows the PLL is locked)

4) running the PFD at 12.5 MHz by disabling the clock doubler and setting B = 6 and A = 12.

 

One thing to note, my LF is not very optimal. I used the high loop BW design from the eval board without first simulating (I know, stupid) with a slight modification. The values are C1 = 62 pF, R1 = 820 Ohms, C2 = 220 nF, R2 = 390 Ohms, and C3 = 33 pF. The value of C2 was modified from 240 nF to 220 nF because I couldn't find a 240 nF part in 0201. The other thing was I bypassed LDO with a 100 nF cap instead of the recommended 220 nF. These can be modified, but I'd prefer not to if not completely necessary (0201 parts were another stupid idea).

 

Any suggestions would be great. What follows is my SPI writes. The first argument is the address and the second argument is the value. Numbers preceded by "&H" are hexadecimal representations while all others are decimal.

 


ADRegEdits.Add({&H10, &H7C})'PLL enable

ADRegEdits.Add({&H13, 6})   'A counter

ADRegEdits.Add({&H14, 3})   'B counter (lower 8 bits)

ADRegEdits.Add({&H17, 180}) 'STATUS pin

ADRegEdits.Add({&H18, 116}) 'VCO calibration divider

ADRegEdits.Add({&H1A, 42})  'LD pin

ADRegEdits.Add({&H1B, 33})  'REFMON pin

ADRegEdits.Add({&H1D, 160}) 'clock doubler

ADRegEdits.Add({&H1E0, 4})

ADRegEdits.Add({&H1E1, 2})

ADRegEdits.Add({&H1C, 2})

ADRegEdits.Add({&HF0, 226})

ADRegEdits.Add({&HF1, 226})

ADRegEdits.Add({&HF2, 226})

ADRegEdits.Add({&HF3, 226})

ADRegEdits.Add({&HF4, 226})

ADRegEdits.Add({&HF5, 226})

ADRegEdits.Add({&HF6, 226})

ADRegEdits.Add({&HF7, 226})

ADRegEdits.Add({&HF8, 226})

ADRegEdits.Add({&HF9, 226})

ADRegEdits.Add({&HF10, 226})

ADRegEdits.Add({&H190, 165})'duty cycle

ADRegEdits.Add({&H193, 165})'duty cycle

ADRegEdits.Add({&H196, 165})'duty cycle

ADRegEdits.Add({&H199, 165})'duty cycle

ADRegEdits.Add({&H232, 1})  'Update Registers

ADRegEdits.Add({&H18, 117}) 'set bit for VCO calibration

ADRegEdits.Add({&H232, 1})  'Update Register (starts VCO calibration)

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