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ADV7441A, Equalization pulses appear to cause pixel clock jitter

Question asked by Mike324 on Jul 16, 2012
Latest reply on Jul 18, 2012 by Mike324

Hello, I have a 480i video source that outputs composite sync on the hsync pin.  This source also add equalization pulses to the composite sync signal, so I get 6 lines of equalization pulses before the vsync, 5 pulses inside the vsync and 4 after the vsync, all the EQ pulses occur at twice the line rate (31.468kHz).  It seams these equalization pulses are causing lots of jitter on my regenerated hsync as well as the pixel clock out of the ADV7441, I observed the jitter with a scope placed on the pixel clock output (LLC).  The STATUS_2 register said the PLL was locked to hsync (bit7 high), so as far as the ADV7441A thought, things were ok.  I'm running this signal through the SDP, I've also tried the CP with no difference.


In the ADI document "ADV7441A_AD9388A_Setting_Recomendations_RevP_140512.pdf" I found under section 2.3.3, that to improve HS jitter on 525P and 625P sources, use this setting: 4E F6 3B.  I decided to give that a shot even though I'm running 480i.  The default value in that register was 0x37, I changed it to 0x3B and it made my pixel clock jitter even worse, so I played with that register, walking the value down to 0x36 and suddenly my pixel clock locked.  My regenerated hsync and DE signals all locked and look clean.

I have two quesions:

1) What is register 0x4E 0xF6 and is it ok to use a value of 0x36?

2) If changing this register is not recommended, what should I do to improve my jitter problems with equalization pulses?