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AD9832 frequency sweep problem

Question asked by ADuCdude on Jul 16, 2012
Latest reply on Jul 18, 2012 by ADuCdude

Dear all,

I've got a problem with the AD9832 DDS chip:

I've build a low frequency DDSgenerator based on the AD9832 DDS. I can use it in CW mode pretty well.

I want to use the chip in  frequency sweep mode as a tracking generator, to do so i continuously reprogram

the next output frequency (every 80ms approx.) without new control word /  initialising.

DDS output power is measured as voltage with a log.-detector chip.

Works fine, but

from time to time i get small gaps in measured voltage as if there is a notch in frequency response -



I tracked the problem down with my scope:

The problem is the output frequency of the DDS occasionally jumps to values way out of my frequency range (9khz...250khz)

as you can see in picture 1 below, channel 3.

i.e: if i sweep the output frequency in 250Hz steps upwards maybe like this :   ... 69.65khz -  69.9khz - 4.xxMhz- 70.4kHz - 70.65khz ....

since my lowpass filter following the DDS rolls off at 500kHz i get the notch like effect in my output signal when it jumps to 4MHz instead of 70.15khz. Additional from time to time the output signal from the DDS switches off completely- output voltage is 0Vdc and no sine wave -

then i have to wake up the chip with reset/initialization.


So why does the DDS occationally behaves this odd ?? -




Picture 1 - Channel 1 (yellow): Clock, Ch2(green): DATA, Ch3 : DDS output


Measurements on Clock and DATA where taken with my oscilloskope. Though i encountered the following

effect - if i probe the Clock line at the DDS pin with my Probe (10:1 , 1MOhm/12pF) the gaps/notches occur far more often,

if i probe DATA line they become more rare -

this leaves me thinking of a timing problem, but as you can see in picture 2 signals are very slow (150khz clock, DDS is rated up to 20MHz SCLK) have all TTL level with steep edges and no ringing. Falling edge of SCLK occurs in the middle of the DATA bit.




Picture 1 - Channel 1 (yellow): Clock 147 khz, Ch2(green): DATA, Ch3 : Fsync


By the way FSELECT, PSEL0,PSEL1 are all grounded -


When i solder 100pF cap onto the DATA-Line the problem seems to vanish , but thats not the

thing i want to do - any comment/ idea to help me understand this behavior ?

Are there any known communication problems with this chip ?