May i get Gated clock (DE.LLC) output from ADV7611 receiver? ie., Line Locked Clock should come only when Data Enable is High.
External circuitry shouldn't add more then one clock delay to the video stream so I'm not sure how this would effect your system since any power up sequence will take much longer then just one pixel clock.
Good question, I don't know the power up sequence of the writes/hs/vs/de/video. I suspect it really depends on the timing between when the between the video, how long the writes take, how long the parts takes to lock onto the video and where exactly the lock within the video stream occurs. Regardless, it will take a bit of time in the lab to get any real test data.
The way I'd set up the processor is:
Of course I don't know what your processor/circuit is so I maybe missing some important details.
Can you explain the application that requires this?
The application for this is to find the Y,Cb and Y,Cr. After the Data Enable went high, the first pixel clock will output the Y,Cb and the second pixel clock will output the Y,Cr. Am going to connect the 16 bit data lines of HDMI Receiver as 32 bit data lines to my processor.
The LLC is an always on clock and can not be gated by the ADV7611. To do this you will use some external circuitry.
You still need to look at HS and VS to determine where the frame begins and ends. Normally DSPs will capture one line based on the HS pulse and DMA that to main memory while it captures the next line.
External Circuitry adds some delay... So it is not a good solution to my logic... Okay... My general question is after powering up and writing all the necessary registers of ADV7611 ... What will come first in the HSYNC output? Is it front porch / Sync/ Back porch ?
Retrieving data ...