I am using an ADV7180 connected to a ADV212 with an NTSC Video Source. The ADV212 is outputting interlaced data. I am operating the ADV212 in 16-bit host mode and accessing the CODE FIFO that way as well.
I have my CODE FIFO Threshold set to 2 32-bit words (i.e. 4 16-bit words) and have noticed that after the JPEG2000 EOC marker 0xFFD9 I read out varying amounts of zero padding after the 0xFFD9 as follows:
XX XX XX XX XX XX XX FF D9 [END]
XX XX XX XX XX XX FF D9 00 [END]
XX XX XX XX XX FF D9 00 00 [END]
XX XX XX XX FF D9 00 00 00 [END]
XX XX XX FF D9 00 00 00 00 [END]
XX XX FF D9 00 00 00 00 00 [END]
XX FF D9 00 00 00 00 00 00 [END]
FF D9 00 00 00 00 00 00 00 [END]
I saw all of the above during one recording session. That is, they were in on file and the different padding lengths occur at somewhat random intervals.
The [END] marks where something else starts such as another image 0xFFFFFFF1 or 0xFFFFFFF0 or no more CODE data was available from the CODE FIFO.
My testing seems to show that there are always an even number of 32-bit words in the CODE FIFO and if the actual image data is not there to fill it, zeros are added to pad it out to make it so.
Base on the diagram below, I wonder if the CODE FIFO is feed by the Internal DMA Engine.
If the Internal DMA Engine is used to feed the code FIFO might there be some DMA transfer block size such as 2 x 32-bit words?
For example the following discusses the use of External DMA (which I an not doing) and mentions 8 x 32-bit word block transfers as well as padding to fill the block size.
I certainly am experiencing padding similar to this when I access the CODE FIFO via the 16-bit host interface.
I have also tried setting my CODE FIFO Threshold set to 4 32-bit words (i.e. 8 16-bit words) and what I notice in this case is that the last few bytes of image data are left in the CODE FIFO (as the threshold is not reached) and I don't end up accessing them until the next image comes in. So really it is not an even number of 32-bit words in the CODE FIFO it is "at least 2 32-bit words".
The makes me believe the Internal DMA transfer must be less that 4 x 32-bit and must instead be something like 2 x 32-bits.
Can someone at Analog Devices confirm this or explain what is actually going on here?
At a minimum, knowing that there will always be at least 2 32-bits words in the CODE FIFO would be very helpful to me.