I am running uclinux on a Blackfin 527. I am always in Full On mode of the Blackfin.
CLKIN = 19.2MHz
PLL multiplier is 20
VCO = 384MHz
CCLK divider is set to 1, so CCLK = 384MHz
SCLK divider is set to 4, so SCLK = 96MHz
I need to change the clock speeds at runtime to save power while remaining in Full On mode.
Using the userspace governor, I can successfully change the CCLK divider to 2, bringing the CCLK to 192MHz. But I can't reduce it further. My goal is to change the CCLK divider to 8 (CCLK of 48MHz) and to bring the SCLK divider to 15 (SCLK of 25.6MHz).
When I look in /sys/devices/system/cpu/cpu0/cpufreq I see that:
cpuinfo_min_freq is 192000
I know that this hardware can run with a CCLK at lower frequencies but how can set the CCLK to something lower? Also how can I change the SCLK divider during runtime?
My config.linux-2.6.x file contains the following:
# Clock/PLL Setup
# CONFIG_PLL_BYPASS is not set
# CONFIG_CLKIN_HALF is not set
# CONFIG_CCLK_DIV_2 is not set
# CONFIG_CCLK_DIV_4 is not set
# CONFIG_CCLK_DIV_8 is not set
# CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_SPEC is not set
I would appreciate any help you can offer.