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Changing CCLK and SCLK during runtime...

Question asked by sbo@schicktech.com on Jul 13, 2012
Latest reply on Jul 20, 2012 by sbo@schicktech.com

I am running uclinux on a Blackfin 527.  I am always in Full On mode of the Blackfin.

 

CLKIN = 19.2MHz

PLL multiplier is 20

VCO = 384MHz

CCLK divider is set to 1, so CCLK = 384MHz

SCLK divider is set to 4, so SCLK = 96MHz

 

I need to change the clock speeds at runtime to save power while remaining in Full On mode.

 

Using the userspace governor, I can successfully change the CCLK divider to 2, bringing the CCLK to 192MHz. But I can't reduce it further.  My goal is to change the CCLK divider to 8 (CCLK of 48MHz) and to bring the SCLK divider to 15 (SCLK of 25.6MHz).

 

When I look in /sys/devices/system/cpu/cpu0/cpufreq I see that:

cpuinfo_min_freq is 192000

 

I know that this hardware can run with a CCLK at lower frequencies but how can set the CCLK to something lower?  Also how can I change the SCLK divider during runtime?

 

 

My config.linux-2.6.x file contains the following:

#

# Clock/PLL Setup

#

CONFIG_CLKIN_HZ=19200000

CONFIG_BFIN_KERNEL_CLOCK=y

# CONFIG_PLL_BYPASS is not set

# CONFIG_CLKIN_HALF is not set

CONFIG_VCO_MULT=20

CONFIG_CCLK_DIV_1=y

# CONFIG_CCLK_DIV_2 is not set

# CONFIG_CCLK_DIV_4 is not set

# CONFIG_CCLK_DIV_8 is not set

CONFIG_SCLK_DIV=4

CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC=y

# CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_SPEC is not set

CONFIG_MAX_VCO_HZ=600000000

CONFIG_MIN_VCO_HZ=50000000

CONFIG_MAX_SCLK_HZ=133333333

CONFIG_MIN_SCLK_HZ=27000000

 

 

I would appreciate any help you can offer.

 

Steve

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