Hi, I'm using multiple AD9125 to generate signals at 70MHz. I use 4× Interpolation 400MHz directly for fDAC and 100MHz for fdata. Digital datapath is PREMOD HB1 NCO , HB2 HB3 bypassed. I use FIFO Rate Synchronization,the DACs output skew to vary from power-on to power-on. BUT when I bypass the NCO and use 560MHz for DAC and 140MHz for fdata the output 70MHz are synchronized. So I think the problem is the NCO of AD9125s are not synchronized. NCO is reset on the first extended FRAME pulse after reg 0x36 bit 4 transitions from 0 to 1. But the FRAME pulse is generated by FPGA can not synchronize with the SYNC_CLK.
In this case how to make the NCOs and outputs synchronized?