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DAC reset and re-intitialisation creates corrupt output spectrum

Question asked by Vishnu on Jul 11, 2012
Latest reply on Jul 13, 2012 by Vishnu

Hi,

 

I’m feeding a digital 12MHz signal from the FPGA to DAC (configured with 8X interpolation, no frequency translation and no NCO) to generate a 12MHz at the output.

I’m using the internal PLL of DAC to run the DAC at 2xDCI. Word mode is used for input data ports.

Inorder to verify the consistency of the output, I reset the DAC and re-configure it, and observe the output. But occasionally, maybe once in 5 times, the output spectrum gets corrupt. Spurious is seen around the 12MHz output.

I suspect some synchronization problem, since if I use an integer multiple of the clock as the output, this problem is not coming.  I’m using a 100MHz DCI, so if feed a 10MHz digital input, this problem is not there.

 

Regards,

Vishnu

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