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Pin Init, Pin INterrupts BF548

Question asked by Johan@Hannes on Jul 10, 2012
Latest reply on Jul 13, 2012 by Prashant
Branched from an earlier discussion

Hi,

 

by now it does not work. Pls. find my code below. One strange behavior more, maybe you can give me a wink one more time....By setting PORT Clear Reg. port set Register is set and port state is read as active, while

no voltage on pin can be measured.Further no interrupt functionallity is provided. Pls. let me know if you need more information....

 

 

/* GPIO definitions */

#define GPIOPA_IAR_SETT *pSIC_IAR2&=~0x0000F000;*pSIC_IAR2|=0x00002000;*pSIC_IMASK0|=(((UINT32)1)<<19);          

#define GPIOPJ_IAR_SETT *pSIC_IAR11&=~0xF0000000;*pSIC_IAR11|=0x20000000;*pSIC_IMASK2|=(((UINT32)1)<<31);          

 

 

#define EBIU_DDRCTL0_DEF       (UINT32)(0x220A840DU)   /* PRQA S 303*/ /* AD definition, DDR CTL 0*/
#define EBIU_DDRCTL1_DEF       (UINT32)(0x10026222U)   /* PRQA S 303*/ /*AD definition,  DDR CTL 1*/
#define EBIU_DDRCTL2_DEF       (UINT32)(0x00000061U)   /* PRQA S 303*/ /* AD definition, DDR CTL 2*/
#define VRCTL                  (UINT16)(0x40DB)       /* PRQA S 303*/ /* AD definition, VRCTL*/

 

 

 

VOID GPIO_InterruptInit()

{

 

   UINT16 u16I=0;

 

   //*pPORTA_FER&=~(PA2|PA3|PA7|PA8);                                              //Clear corresponding MUX Reg,use Pin as GPIO                                                  

   *pPORTA_DIR_CLEAR =(PA2|PA3|PA7|PA8);                                        //Set DDR Reg.

   *pPORTA_INEN =(PA2|PA3|PA7|PA8);                                             //Input enable

 

   //*pPORTJ_FER&=~(PJ1|PJ2|PJ5|PJ6);                                              //Clear corresponding MUX Reg,use Pin as GPIO                                                  

   *pPORTJ_DIR_CLEAR =(PJ1|PJ2|PJ5|PJ6);                                        //Set DDR Reg.

   *pPORTJ_INEN =(PJ1|PJ2|PJ5|PJ6);                                             //Input enable

 

   //Port A

   *pPINT0_ASSIGN = B0MAP_PAL|B3MAP_PAH;

   *pPINT0_MASK_SET = PA2|PA3|PA7|PA8;

   *pPINT0_EDGE_SET = PA2|PA3|PA7|PA8;

   *pPINT0_LATCH = PA2|PA3|PA7|PA8;

 

  

   //Port J

   *pPINT3_ASSIGN = B0MAP_PAL;

   *pPINT3_MASK_SET = PJ1|PJ2|PJ5|PJ6;

   *pPINT3_EDGE_SET = PJ1|PJ2|PJ5|PJ6;

   *pPINT3_LATCH = PJ1|PJ2|PJ5|PJ6;

 

 

   GPIOPA_IAR_SETT                                                    //Interrupt assignement Reg.Lvl.9

   GPIOPJ_IAR_SETT                                                    //Interrupt assignement Reg.Lvl.9

  

   (VOID)register_handler(ik_ivg9, (GPIO_ISR));                      //Register interrupt handler

   ssync();

}

 

VOID CPU_Init (VOID)

{

  ADI_SYSCTRL_VALUES tSysCtrl; 

 

  // program the PLL for a 400MHz Core CLK, and 100MHz SCLK

 

  //(based on CCLK = CLKIN*MSEL; SCLK = CCLK/SSEL; here: MSEL = 16, SSEL = 3 and CLKIN = 25MHz)

 

  tSysCtrl.uwPllCtl = PLL_MSEL_VALUE<<9;

 

  tSysCtrl.uwPllDiv = PLL_SSEL_VALUE;

 

  tSysCtrl.uwVrCtl  = VRCTL;

 

  //response will not be handled, since not necessary

  (void)bfrom_SysControl( SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV  | SYSCTRL_VRCTL | SYSCTRL_INTVOLTAGE, &tSysCtrl, NULL);

    ssync();

 

  // configure the EBIU based on calculation from 'Firmware/Doc/BlackfinRegisterCalculations.xls'

  *pEBIU_DDRCTL0 = EBIU_DDRCTL0_DEF;                       /* PRQA S 303,1281*/ /* AD definition*/

  *pEBIU_DDRCTL1 = EBIU_DDRCTL1_DEF;                       /* PRQA S 303,1281*/ /* AD definition*/

  *pEBIU_DDRCTL2 = EBIU_DDRCTL2_DEF;                      /* PRQA S 303,1281*/ /* AD definition*/

  

  ssync();

}/*CPU_Init*/

 

EX_INTERRUPT_HANDLER(GPIO_ISR)

{

   /* clear interrupt request */   

   UINT32 u32Temp;;

  

  

  

   //PINT0 Interrupt source,PAH/PAL

   if(IRQ_PINT0&*pSIC_ISR0)

   {

   

      u32Temp=*pPINT0_LATCH;

      *pPINT0_REQUEST = u32Temp;          //Clear Interrupt

     

      //Check which pin asserted the ISR

      if(u32Temp&PA2)

      {

         *pPINT0_LATCH|=PA2;  //Clear PINT request to avoid recurring interrupts

         u32CountGlob++;

      }

 

      //Check which pin asserted the ISR

      if(u32Temp&PA3)

      {

         *pPINT0_LATCH|=PA3;  //Clear PINT request to avoid recurring interrupts

         u32CountGlob++;

      }

      //Check which pin asserted the ISR

      if(u32Temp&PA7)

      {

         *pPINT0_LATCH|=PA7;  //Clear PINT request to avoid recurring interrupts

         u32CountGlob++;

      }

        

      //Check which pin asserted the ISR

      if(u32Temp&PA8)

      {

         *pPINT0_LATCH|=PA8;  //Clear PINT request to avoid recurring interrupts

         u32CountGlob++;

      }            

  

   }

  

   //PINT3 Interrupt source ,PJH/PJL 

   if(IRQ_PINT3&*pSIC_ISR2)

   {

      u32Temp=*pPINT3_LATCH;             

      *pPINT3_REQUEST = u32Temp;          //Clear Interrupt

     

      //Check which pin asserted the ISR

      if(u32Temp&PJ1)

      {

         *pPINT3_LATCH|=PJ1;  //Clear PINT request to avoid recurring interrupts

         u32CountGlob++;

      }

 

      //Check which pin asserted the ISR

      if(u32Temp&PA2)

      {

         *pPINT3_LATCH|=PJ2;  //Clear PINT request to avoid recurring interrupts

         u32CountGlob++;

      }

      //Check which pin asserted the ISR

      if(u32Temp&PJ5)

      {

         *pPINT3_LATCH|=PJ5;  //Clear PINT request to avoid recurring interrupts

         u32CountGlob++;

      }

        

      //Check which pin asserted the ISR

      if(u32Temp&PJ6)

      {

         *pPINT3_LATCH|=PJ6;  //Clear PINT request to avoid recurring interrupts

         u32CountGlob++;

      }                     

     

   }

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