i'm using an ADF4118 as a clock multiplier to get a 10MHz VCXO locked to a 20KHz reference signal.
The phase detector frequency is 100Hz and the loop filter is of the active type with a passive pole at the output;
the non-inverting input of the opamp (rail to rail input and ouput, vdd=5V vss=0V) is biased at 1/2 vdd=2.5V.
PFD gain is 1mA.
I made several tests, changing pfd current gain and loop parameters, and i get in the reality
almost the same results as your adisimpll. Very good!
Finally, an on board 20KHz generator is automatically connected to the reference input of the pll, in case
the input 20KHz signal amplitude is below a certain threshold.
The strange behaviour i noted is this: if i power up the circuit, the pll locks in, more or less, the time
specified by the program, in my case about 8 seconds (i don't need quicker times, 8 / 10 seconds is fine)
and the time is the same if it is locked to the internal or external reference source.
But if i remove the external source or suddenly change its frequency by some hundreds of hertz, just to
check the system behaviour when the input is perturbed, it may happen that the loop filter is driven to
any of the two output rails, 0V or 5V, and here remains for about 40 seconds before locking again.
It does not seem a sort of opamp latchup since, at the charge pump output, the voltage remains
almost stable (it seems to go periodically towards the locking voltage then back again to the previous value)
then, suddenly after 40 seconds or more, it gets locked again.
Nothing changes is i turn the pfd output current to 250uA or 1mA or i change the pfd frequency,
apart the obvious differences in loop response, nothing changes if i reset the pll registers sending
a pll-init sequence when the mcu finds the loop unlocked.
For the final application, this overall behaviour would not be bad and i could consider this design as completed,
but i was really curious if i'm missing something and there is a solution for this.